The present invention relates to a method and/or architecture for tristate busses generally and, more particularly, to a method and/or architecture for a multilevel circuit implementation for a tristate bus.
In the construction of electronic circuits, many designers use programmable logic devices such as field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs) to implement digital circuit designs. Using a programmable logic device can reduce the amount of time between the conception of a circuit design and the production of a working circuit prototype, as well as facilitating later design changes. However, the utility of a programmable logic device for implementing large and/or complex logic functions may be limited by a lack of appropriate logic circuitry. Specifically, the number of drivers that may be supported on a single line or bus in some programmable logic devices is typically limited by a fixed number of tristate buffers in the device architecture.
Some programmable logic devices have multiple lines. However, the number of tristate buffers associated with any one line is fixed, placing a maximum on the number of drivers that can drive each line. The utility of the device in applications having a large number of drivers driving a common line or bus is diminished once the number of drivers becomes very large or the tristate bus runs over a large physical area. However, by splitting a large tristate bus into a number of lines to form a multilevel tristate bus, an apparent increase in the tristate buffer limit may be achieved. Examples of combining lines to form wide busses may be found in U.S. Pat. No. 5,973,506.
Referring to FIG. 1, a circuit diagram illustrating a multilevel tristate bus 10 is shown. The tristate bus 10 has two lines 12 and 14. Each of the lines 12 and 14 has three tristate buffers 16a-16c and 16d-16f, respectively. The line 12 is connected to a first input of an AND gate 18. The line 14 is connected to a second input of the AND gate 18. The lines 12 and 14 are resistively coupled to a supply voltage VCC via pull-up resistors 20 and 22, respectively.
Due to the effects of pull-up resistor 20 and 22, lines 12 and 14 default to a HIGH logic value in the absence of a low impedance path to ground from any one of the tristate buffers 16a-16f. Because the tristate buffers 16a-16f present a high impedance if any one of the tristate buffer control inputs is LOW, the logic value of the lines 12 and 14 is HIGH if logic inputs to the tristate buffers 16a-16f are HIGH or if the control input of the tristate buffers 16a-16f are pulled LOW. The wired function provided by the connection of the tristate buffers 16a-16c and 16d-16f is therefore equal to an AND function. By connecting the lines 12 and 14 with the AND gate 18, the multilevel implementation acts like a single line with twice the number of tristate buffers. When one of the tristate buffers 16a-16f is enabled, a corresponding input signal (e.g., IN0-IN6) is communicated to an output 24 of the AND gate 18. To avoid contentions, only one of the tristate buffers 16a-16f is enabled at a given time.
Each tri-state driver is connected to a signal source. Only one driver drives at a time, and the rest are disabled. For a large number of sources, each buffer has to drive a large load. Driving a large load makes the signal conduction very slow.
The lines 12 and 14 are coupled to VCC via the pull-up resistors 20 and 22. The pull-up resistors 20 and 22 may, for example, be implemented with a NMOS transistor having a gate tied to VCC or with a PMOS transistor having a gate tied to ground. The current sourcing ability of the pull-up resistors 20 and 22 are designed to be weak relative to the current sinking ability of any single tristate buffer 16a-16f coupled to the lines 12 and 14. The weak current sourcing ability of the resistors 20 and 22 permits the tristate buffers to pull the lines 12 and 14 to a LOW logic value more quickly. When a buffer on line 12 is disabled and a buffer on line 14 is enabled, the weak pull-up of the resistor 20 can be very slow pulling the line 12 HIGH.
The present invention concerns an apparatus comprising a first circuit and a second circuit. The first circuit may be configured to drive a first bus in response to a first control signal. The second circuit may be configured to control a voltage level of the first bus in response to the first control signal.
The objects, features and advantages of the present invention include providing a method and/or architecture for a multilevel circuit implementation for a tristate bus that may (i) decrease a load on drivers connected to a bus, (ii) speed up the critical path, (iii) allow new data from another net to be placed more quickly on a bus and/or (iv) increase speed with little additional cost in area or power.